1. Technical Field
The present invention relates to a multi-layered printed circuit board and a manufacturing method thereof.
2. Background Art
General fabrication processes of printed circuit boards involve a process of forming a plurality of wired patterns on a substrate, a testing process of checking the quality of each wired pattern, a process of packaging quality-approved printed circuit boards and a process of putting the packaged printed circuit boards in a final test.
Here, the testing process, in which electrical properties of the wired patterns are tested, includes a process of giving an open/short test (OS test) to the wired patterns. Currently, a widely used process of performing the OS test for the fabricated wired patterns relies on a probe instrument equipped with probe pins that are electrically accessed to the wired patterns.
Meanwhile, testing for open-circuit in the wired patterns is only possible if there are at least two test points, but there may be only one test point connected to an outside, depending on the type of wired pattern.
Accordingly, in case there is only one test point, it is difficult to pre-detect the open-circuit, and the defect is inevitably discovered in the final product. Therefore, there has been a demand for measures that enable a test for the wired pattern even if there is only one test point.
The related art of the present invention is disclosed in Korea Patent Publication No. 10-2014-0042326 (laid open on Apr. 7, 2014).